VLSI Tidbits

Hi folks,
I have started this blog for discussion on Seq ckt timing, FSm design.

Guys I don't want to waste ur time and mine too , with
What is a FF? what is a Latch? Differentiate them.....etc.....I hope you understand basics......

Coming to a Fundoo Question.......all of u know Setup time and hold times .....but why these exist
(certainly not to make a design engineer break his head in STA ).

A FF at ckt level is implemented using either TGs or NMOS Txs in MOS technology. For proper functionality of the ckt certain requirements/constraints are to be satisfied. Setup, hold times are such constraints. A FF can be implemented in a static way or dynamic way. Static implementation relies on regenerative feedbak to store data whereas dynamic implementation relies on capacitance to store data as charge ( presence or absence of charge ). Charge is lost in due time due to leakge currents and needs to be refreshed periodically, the interval depends on leakage current. Still Dynamic implementation is used in places where data changes rapidly due to the simplicity and high density dynamic implementation offers.

Why Setup/Hold times?
A FF at circuit level is implemented as a cascade of two latches, one active high and the other active low. A positive edge triggerd FF is realized with a active low latch followed by active high latch.Data is sampled at Positve edge. Acive low latch is transparent when clock is low but active high latch is transparent when clcok is high. Data at the i/p of a active low latch (at positve edge) stays at the o/p ( after positive edge latch is not transparent ) and data to the i/p of active high latch is this sampled data. So, data that is passed from i/p to o/p of a +ve edge triggered FF is the data that is presnt at the positve edge.

Open in a new window
http://www.geocities.com/reddysarchive/vlsi/Latch.JPG
Please draw the second half and analyze..
Please bear with me I am not a good artist....... I hope you could find TG and inverter.....

For proper sampling of data, sufficient time must be allowed for the cross coupled inverter pair to reach a valid state. In the ckt , say clock is low and it is going to high , we encounter the positive edge , here comes the setup time requirement. TG(clk_bar ) is say closed as clock is low and by the positive edge arrives data at inv3 o/p and data at inv2 i/p should be same , i.e data must have proagated from D i/p to the o/p of inv3, Path is D-->TG(clk_bar)--->inv2--->inv3. Now after clock edge TG(clk ) is closed and data is held by cross coupled latch pair. So setup time for this FF circuit is Tsetup= 3T(inv) + T(TG).

Hold TIme: In the ckt, if clock goes high TG(clk_bar ) is open and any change occuring at D after positive edge does not propagate into the circuit, so hold time is zero.

Propagation delay,Tclock-to-Q, Tpff: inv2 has already reached it steady state , this time has been included in setup time so delay for clcok- to - Q is delay of two inverters and a TG ( for visualization draw the second half of FF . ( path from Q-intermediate to inv3 of second half + lower TG of second half + inv2 of second half ) ( the path ends at Q) ( inv3 of second FF and TG upper are not considered in Tclcok-to-Q ).

Hope this is clear.... If anybody could not get the point or if I am not clear plese lemmeknow.

I need your comments, they give me boost for future work....

Coming next

*Calculating Max Clock frequency in Seq Ckts....
* Metastability .....
* FSMs.....

How to Calculate Maximum Clock Frequency in a seq ckt?

Well by this time, I hope you understood setup,hold time and Tclock-to-Q parameters for a FlipFlop.

In a Latch there is an additional parameter T(D-to-Q): this is the delay for the change at input D during the active clock period: high or low,whatever it is , to reflect at the output.

Tclock-to-Q is the delay from active clock level to the instant where the ouptut changes considering that data is not changing.

Now let's discuss the case of seq ckts with FFs


Consider two D FFs A and B cascaded together...

http://www.geocities.com/reddysarchive/vlsi/flip_flop_dual.gif

and assume a clock waveform , name the positive edges of clcok p1,p2,p3 and so on.......
negative edges n1,n2,n3 and so on.....

Now you know that there exist Tc-q ( Tclcok-to-Q , from now onwards Tc-q)
Tsetup.

The essense of Sequential logic : At every clock edge/ sampling instant a FF's output is the input that it has at it's D input in the previous clock period.

Suppose D i/p has a change at Tclock-low and this data is sampled only in the next clock period i.e: at the active clock edge of next cycle.

Now see the figure
FF A gets data D1 at say clcok edge p1 ( assuming setup constraint is satisfied i.e: D1 is available Tsetup before the positive edge p1 and is stable), it takes Tc-q time to propagate to o/p.
and it can be sampled by FF B properly, at postive edge p2, if it's setup time constraint is met.

So a total amount of time = Tc-q of FF A + Tsetup of FF B should be provided for proper operation of the circuit.

The time actually available for this is the time between p1 and p2.

So Tp1-p2 sholud not be less than : Tc-q (FF A) + Ts ( FF B).

i.e : Tclk >= Tc-q (FF A ) + Ts ( FF B)
this places a constraint on the minimum period of clock, the minimum period bieng
Tc-q(FF A) + Ts ( FF B ).

This actually is the constraint placed on the Maximum clock frequency.

Now come to the Hold time constraint......

suppose D1 is latched by FF AA at p1 and Tc-q of FF A is less than Thold of FF B,
what happens?
hummmm There is chance that this change in D i/p may be completely reflected of cause a invalid logic level at the o/p of FF B. ( At this time ,p1, FF B is sampling the o/p of FF A corresponding to the edge p0 ( previous one of p1)). So data D0 ( corresponding to D0 ) is lost.

so, data should not change upto Th ( Thold) from the edge p1.

This actually is called hold violation and is said that a race condition has occured.

This can be stated as a hold constraint
Tc-q > Th

suppose Tc-q is varying between 3ns and 1 ns , worst case situation is considered and
Tc-q,min is to be considered....
so
Tc-q,min > Th
Now suppose there is some combo logic between FF A and FF B i.e between Q o/p of FF A and D i/p of FF B.

while considering Tsetup constraint an additional time of Tcombo should be taken into account.

i.e: Tclk >= Tc-q( FF A ) + Tcombo + Tsetup ( FF B)

considering worst case Tcombo,max is taken

so,
Tclk >= Tc-q(FF A ) + Tcombo,max + Ts ( FF B).

and coming to hold constraint......
The minimum delays Tc-q,min and Tcombo,min should be more than Th ( FF B ) else data changes before an interval of Thold ( from clock edge p1) and this may get reflected at o/p of FF B.
so,
Tc-q,min + T combo,min >= Thold.

Hold violation leads to system failure.

Setup violation places a limit on maximum Clock frequency that can be used.

Now suppose O/p of FF B is fedback to i/p of FF A via some combo logic.

then another path from FF B to FF A is to be considered and two equations for setup and two for hold time constraints are to be considered and worst case values are considered.

for path2, FF B to FF A
setup constraint : Tclk >= Tc-q ( FF B) + Tcombo,max + Ts ( FF A)
hold constraitn : Tc-q,min (FF B ) + Tcombo,min > Thold .

In general there is some combo logic between FF s and this ensures that hold constraint is met.

To sum up ,
Ts places limit on maximum clcok frequency and Thold has nothing to do with Clock frequency ( in FF based designs ). What ever may be the clock frequency , if Tc-q and Tcmbo are very small there is a chance that hold violation occurs.


Hope I am clear , if you find this interesting or helpful, please lemme know...


coming up .......
clock skew and it's effect on Tclk,min/ Fclk,max.

5-03-2005.......

What is clock skew?
Clock skew is spatial variations of the clock signal.
CLock jitter is temporal variation of clock signal.

Suppose there are various points where clock is needed, consider two nodes i and j ,
say clock edge occurs at node i ant time T and at node j at T+delta.
Skew between nodes i and j is defined as t(j) - t(i) = delta.

Jitter is defined in time domain.
At a point clock edges should appear at intervals of T seconds.....assuming clock period of T seconds........i.e: +ve clock edges should occur at integral multiples of T ( -ve edges also )
Suppose at point "i" clock edge appears at "nT-delta" instead of "nT" and at "(n+1)T-x"
then a jitter of "delta" at nT and "x" at (n+1)T is said to have occured.
the worst case jitter is max(delta,x), note jitter is defined in time domain ( temporal)
and skew is defined in spatial domain
Suppose clock cycle 10 occurs at node i at T seconds and at node j at T+x seconds, then clcok is said to be skewed.....skew bieng x seconds.

Now coming to the effect of skew on Max Clcok Freq.......
Once again take the case of two cascaded FFs , and assume a skew of " x "between FF A and FF B. This allows more time for the data to propagate from FF A to FF B because FF B has it's clock delayed. This in effect is same as increaing clcok period.

Now suppose without skew min clock period is 10 ns and clock i/p to FF B is skewed by 1ns
At FF A clock edge occurs at T ns and time given for o/p at FFA to propagate to FF B is T+10 ns (FF B samples o/p of FFA in the next cycle) i.e : by T+10 ns data should propagate to i/p of FF B.

Now with skew of 1ns , clock edge appears at T+11ns, so 1 ns more is available.
So, Tmin is now 11 ns instead of 10 ns.

Tclk + skew >= Tc-q + Tcombo,max + Ts
or
Tclk,min + skew = Tc-q + Tcombo,max + Ts

Tclk,min = Tc-q + Tcombo,max + Ts - skew.

It is apparent that Tclk,min is now reduced that is maximum clock frequency is increased.

Coming to hold requirement, clock edge occurs late so data should be held constant for long time than in the case without skew.
so
Th + skew < skew =" 2ns," min =" 2ns" min =" 1ns," th=" 2ns"

Labels: digital design logic vlsi